FPGA Design

CSE offers FPGA/CPLD design and development services for a variety of vendors (ALTERA, Microsemi, XILINX).

The services include part or all of the following:

  • Wish list/concept captured in a Requirements Specifications document that is approved by the customer prior to any design/development work
  • Proposed vendor/family of the FPGA/CPLD to be used
  • Design Specification document
  • HDL (VHDL/Verilog) or schematic based design capture/development per customer requirement
  • Extensive Design simulation (functional, timing, power)
  • Complete Data sheet per FPGA/CPLD for efficient use by the customer’s team
  • Design Test/Verification on board level

The FPGA/CPLD design services offered include RTL coding in VHDL/Verilog, simulation and verification of models and memories, processors and peripheral devices. CSE is continuously optimizing its tools, procedures and processes in order to provide cost effective state-of-the art turnkey integrated embedded solution systems keeping pace with technology progress and customer requirements.

Our team has 20+ years of experience in:

  • VHDL / Verilog design
  • From simple glue-logic to advanced functions, interfaces, algorithms, IP cores.
  • Performance optimization on embedded systems running on MPUs/MCUs (e.g. design re-partitioning for bit-wise, time consuming calculations, power consumption reduction with low-power CPLDs etc)
  • Replacement of legacy systems/sub-systems/HWCI with the use of FPGAs/CPLDs.
  • Test bench development & Verification
  • Complete FPGA development life cycle support from Specification through RTL and Synthesis to fully tested device including the target board.
  • Proof-of-Concept on CSE’s custom, user furnished or market available (evaluation) board(s).

All engineering design processes, development life cycle, technical reviews and documentation are handled per IEEE 1220-2005.

To discuss your technical requirements, please contact support@creativese.eu.

Crative Systems Engineering

Crative Systems Engineering

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